DESIGN OF AREA AND POWER-OPTIMIZED VLSI ARCHITECTURE OF ALUDESIGN USING SIGNED MULTIPLIER

Technology in this digital age relies on Arithmetic Logic Unit (ALU) procedures to determine the system performance. Due to the fact that, the ALU is a necessary component of any Central Processing Unit (CPU), and its importance is equal to that of the computer CPU. In order to increase the device flexibility and reusability, this work deals with the design of a 32-bit ALU utilizing a structured Hardware Description Language (HDL). In addition, a signed multiplier and a few more additional arithmetic and logical functions are used to create ALU's logic.This research focuses on the multiplier's optimal design, by directly recoding the total to its Modified Booth's (MB) form.The MB encoding unit is converted into a single data route block. There is just one adder at the conclusion of the add-multiply (AM) component (final adder of the parallel multiplier), which in turn, the recoding process critical routelatency is decreased and decoupled from the bit-width of its inputs. In this paper, a novel method for direct recoding of two integers into the MB form is presented and ALU is implemented in Verilog HDL, synthesized by Xilinx ISE 14.7.It is observed that, there is no significant increase in area, power, and delay overhead.