Implementation of Unbiased Rounding for 64-Bit Floating Point Adder

Rounding is mostly performed on floating point numbers. Rounding can be made simpler by using HUB format. The HUB based floating point adder is termed as Architecture A. But some bias may be introduced by using the HUB format. Bias occurs while rounding post truncation, when all the bits to be discarded are zeros. This scenario is called a tie condition. A tie condition occurs while rounding in floating-point related operations. The architecture to partially eliminate the bias is proposed in this paper by making slight modifications to the existing HUB floating point adder. The proposed architecture is termed as Architecture A+. FPGA implementation of three architectures - 64-bit conventional adder for floating point numbers, Architecture A and, Architecture A+ have been done. FPGA implementation results of partial unbiased HUB adder for floating point numbers is compared with 64-bit conventional adder for floating point numbers. The results show that the delay has decreased from 0.197ns to 0.182ns (8.24
^%
), power has reduced from 0.94W to 0.86W (9.3
^%
). Along with these the number of LUT's used have decreased from 2894 to 2315 (25
^%
). Hence, the partial unbiased HUB adder is better than conventional floating point adder.