Implementation of N-bit Universal BIST for Testing of Memory and Arithmetic Operator Using FPGA

A Linear Feedback Shift Register is very widely used in Built-In Self-Test (BIST) and encryption applications. It is one of the finest pseudo-random number generators to test various devices such as Micro-Processors, Micro-Controllers, DSP processors, Arithmetic operators, and Memory devices. To test different bit size modules each BIST module with a respective bit size need to design, which leads to an increase in design time, validation of individual BIST, and also the cost of production. A novel design of N-bit Universal BIST for Testing Arithmetic and Memory devices is implemented with run-time configurable from 2-bit to 32-bit sequences. The design target is to minimize the latency and various design constraints. The logic will be implemented in such a way only one LUT will be storing different tap point equations to reduce the BRAM and CLB's utilization at FPGA