A Comparative Analyze of FinFET and Bulk MOSFET SRAM Design

FinFET technology has become the most popular topic in submicron SoC and VSLI design in recent years, attributable to its numerous advantages, including excellent scalability and low power consumption. This paper aims to provide a comparative study on the performance of FinFET SRAM and bulk MOSFET SRAM. Five architectures (6T, 7T, 8T, 9T, 10T) of conventional CMOS SRAM are investigated in this paper to understand the existing constraints on bulk MOSFETs in nanoscale integration. The options for replacing the bulk MOSFETs were evaluated, including DG SOI (Double Gate Silicon on Insulator) MOSFET, and FinFET. Then this paper elaborated on the benefits of incorporating FinFET into 6 - 9T SRAM configurations and explored the possibility of SRAM topology with the independent gate (IG) FinFET, while the potential drawbacks of FinFET technology are also discussed at the end. With the scaling down of transistors and increasingly demanding lower power devices, FinFET proved its irreplaceable significance in the future SRAM design.