Efficient FPGA Implementations of Lifting based DWT using Partial Reconfiguration

Discrete Wavelet Transform (DWT) is an ubiquitous mathematical technique used in a wide range of applications. The fundamental advantages of DWT are its high compression ratio, lack of blocking artifacts, and strong time & frequency domain localization. This proposed work is an efficient implementation of (9,7) lifting based 1D, 2D, and 3D DWTs, where the hardware software codesign with partial reconfiguration (PR) has made a significant reduction in resource utilization. Additionally, the suggested approach yields a very low mean square error (MSE), resulting in a substantially higher peak signal to noise ratio (PSNR). The constant multiply-add unit based proposed work with single core implementation achieves 80% decrease in the number of look up tables (LUT) and 32% decrease in number of slices utilized when compared with the variable multiply-add unit based implementation. To prove the architecture's originality, it is tested for six distinct applications such as mono audio, stereo audio, grayscale image, colour image, gray scale video, and colour video. The implementation of the work is done on Zynq 7000 (XC7Z020CLG484-1) field programmable gate array (FPGA) with Xilinx Vivado.