A Time-to-Digital Converter Based on Looping and Averaging Logic for Accuracy Improvement

In this work, a time-to-digital conversion (TDC) circuit based on loop measurement for accuracy improvement is proposed. The structure is based on a coarse counter and two-stage interpolator, using different phase-locked loops (DLLs) to obtain polyphase signals that are insensitive to PVT changes and precise adjustment of the delay in the vernier delay loop to improve conversion linearity Spend. The loop control circuit loops the input signal multiple times and generates a control signal to allow the TDC array to receive the pulse signal in an orderly manner. The realization is to use a small number of TDC channels instead of big TDC arrays to cycle a single time interval at the same position in different reference clock cycles. These clock cycles are then distributed to different channels of the TDC for measurement, and the difference between the channel results of multiple groups of START and STOP are averaged to reduce the impact of clock jitter caused by external random noise for the accuracy improvement of the TDC. The circuit and the chip layout were implemented using a conventional 0.18μm CMOS process and the post-layout simulations were carried out. Simulation results show that with the dynamic range of 1280ns, the TDC achieved a single-shot accuracy of 7.29ps and the total power is about 9.53mW. The peak value of differential nonlinearity (DNL) of the START and STOP interpolators is less than 0.017LSB and the integral nonlinearity (INL) is less than 1.7ps.