A Programmable Gain Dynamic Residue Amplifier in 65nm CMOS

This paper presents the schematic and layout design of a fully differential dynamic residue amplifier in 65 nm CMOS technology, with application in a 2-stage SAR-pipelined ADC. A programmable gain is obtained varying both the common-mode current and the amplification time window. The design is verified through post-layout simulations for different PVT conditions. The amplifier achieves a configurable gain A
v
= 4 ± 15 % with a power consumption range {39–61} μW. For A
v
= 4, the input referred noise is σ
n
= 93 μV while the distortion is negligible, resulting in an effective number of bits (ENOB) = 5.9 bits. The random offset due to fabrication process mismatches is σ
os
= 5.8mV.