One Shot System Based Reliability Modelling And Analysis for Low-Cost Fault-Tolerant Computing System Comprising of One Instruction Cores

Rapid CMOS device size reduction resulted in billions of transistors on a chip have led to integration of many cores leading to many challenges such as increased power dissipation, thermal dissipation, occurrence of transient faults and permanent faults. In a multi-core scenario, the mitigation of transient faults and permanent faults at the core level using redundancy-based fault mitigation technique thereby improves the reliability of multi-core systems. In an asymmetric multi-core system, the smaller cores provide fault tolerance to larger cores is a core-level fault mitigation technique that has gained momentum and focus from a large number of researchers. The paper presents an economical, asymmetric multi-core system consisting of one instruction cores (MCS-OIC). The term “Low Cost” signifies power and area consumed by MCS-OIC. In MCS-OIC, MIPS cores are the conventional core and OICs are support standby redundant core. OICs pro-vide functional support to conventional cores for shorter periods of time. Failure in Arithmetic Logic Unit to execute instructions result in transfer of operation codes to OIC. OIC executes failed instructions by the repeated execution of one instruction named “subleq”. The behavior of OICs in MCS-OIC is modelled using a One-Shot System (OSS) model for reliability analysis. The OSS based reliability model allows effectively map the model parameters to core-level and functional-level probabilities to estimate the system reliability. Increase in number of OICs results in enhancement system reliability is validated using simulation results, thereby scalability of the MCS-OIC is observed.