Low Power High-Speed Optimized Comparator for Flash ADC

This paper presents an optimized latch-based Comparator architecture for 70–75 MS/s, 8-bit, CMOS Analog to Digital Converter (ADC). To achieve enhanced performance specifications of the latch-based comparator, the design specifications of the comparator are modified up to optimum levels hence flash ADC architecture. Resulting in limiting power dissipation and delay of comparator i.e., 0.21mW and 4.36ns respectively are achieved. Subsequently, the sampling speed 150MHz (min.) at an analog power supply of 2V with a total power consumption of 7.27mW at full speed is achieved. The modified preamplifier architecture scales down the power consumption and supply of the entire ADC architecture as well. The comparator is implemented using a
$\boldsymbol{0.35\mu} \mathbf{m}$
CMOS technology node using the Cadence Virtuoso tool.