Modeling of a Digital $\mathrm{V}^{2}$ Controlled Buck Converter

V
²
controllers are popular in the industry and academia owing to their simple control loop implementation and fast load transient response. However, transient performance and fast-scale stability status depend on the effective series resistance (ESR) of the output capacitor. In many applications, a large ESR of the output capacitor is not acceptable due to large ripple voltage at the output and poor efficiency. However, a small ESR makes the poles complex conjugate, thus, transient performance degrades. Using an average model, this paper derives an analytical expression of minimum ESR to make the closed-loop poles real. The minimum ESR boundary varies if the input voltage or compensating ramp slope changes. Based on the ESR boundary, designers can choose the right controller to enhance stability boundary and transient response of the buck converter. A prototype buck converter is fabricated and the analytical boundary is validated experimentally.