Analysis of Low-Delay in 64-bit Vedic multiplier based MAC unit

Delay becomes crucial part in any of the considered condition to build any integrated circuit. As delay indirectly dictates speed which means less delay, speedier working environment of circuits and vice versa which is why it is considered as main option along with other side options of parameters like power, area etc. In any processors, its speed depends upon its internal units. So, to meet the standards, A high speed MAC unit is developed and the details regarding it are explained in this paper. This MAC unit performs operations like multiplications, addition and many more required to the application. To implement this model, we write a Verilog code for total unit along with individual units and use Xilinx tool and model sim simulator. The results here show how much delay is reduced compared to other models of MAC unit. The proposed system can be implemented in FPGA Spartan 3 XC3S 200 TQ-144.