Noise Margin analysis of Efficient CNTFET- based Standard Ternary Inverter

Low-power circuit designs are required for battery-operated devices. A transistor needs to be small enough to be integrated onto a single chip. Therefore, CNTFET technology has been widely used to design nanoscale circuits for energy-efficient integration. Multiple-valued logic is utilised to reduce the circuit complexity by minimizing the interconnections. Compared to binary circuits, MVL circuits are more noise sensitive. As a result, it’s essential to consider noise margin into account when designing sustainable and reliable ternary circuits. The paper proposes a standard ternary inverter and compares noise margin, power consumption, delay, and PDP measurements with existing standard ternary inverters. The proposed STI has a 68.6% higher noise margin than the existing designs and 82%, 80%, and 91% improvements in power consumption, PDP, and delay, respectively, over existing circuits.