Layout Design and Analysis of UWB Gaussian Pulse Transmitter Using 90nm CMOS Technology

The layout design of a low-power ultrawideband (UWB) transmitter is proposed with the basic building blocks having a voltage-controlled ring oscillator (VCRO), modulator and pulse generator using 90-nm CMOS technology in Cadence Virtuoso using a smaller number of transistors and passive elements. Frequency is generated using a ring oscillator with a common-gate switching nMOS to vary the delay. Here, 5 GHz to 7 GHz frequency is generated by controlling the voltage from 1 V to 5 V. Moreover, adding capacitors with VCRO having different capacitance values can also generate a different range of frequencies. Due to the higher efficiency of BPSK modulation technique over other techniques, it is implemented here in the proposed transmitter model. A very compact high-frequency BPSK design is proposed for the modulation circuit. Then, a Gaussian second-order pulse with 135ps width is generated for effective transmission of data. Gaussian pulse with varying widths can also be generated using the proposed model. The maximum sizing used for the transistors does not exceed 2 $\mu$m. The post layout simulation results show the better performance of the transmitter in case of power consumption which is S29.51 $\mu$W, energy efficiency where energy per bit is 3.74 pJ/b, and output pulse width which is 135ps over the other existing UWB transmitters.