Design of Adiabatic Logic Two Tail Comparator for Low Power and Analyze with CMOS Comparator

The purpose of the research is to develop an innovative Adiabatic logic two tail comparator, analyze its power utilization and compare it with Complementary Metal Oxide Semiconductor (CMOS) logic two tail comparator. Tanner tool EDA is used to simulate and check the comparator's configuration. The length of transistors in a circuit was varied to obtain power values. The innovative adiabatic logic double tail comparator was found to consume power of 0.43mW. The significance of the study is around 0.000 which is less than 0.05 (p<0.05). Compared to the adiabatic logic two tail comparator, the developed CMOS logic two tail comparator shows low consumption of power.