Thermal characteristics analysis and optimization of 3D-Stacked Memory Packaging

With the increase of power consumption and running speed, the junction temperature of three-dimensional stacked memory devices has increased. It eventually leads to chip overheating and may cause device failures. It is essential to analyze and optimize the thermal performance of the package. In this paper, the finite element analysis method is used to study the influence of the package module on the chip junction temperature and thermal resistance for the typical six-layer stacked memory chip packaging structure. The main influencing factors are investigated. In addition, the thermal characteristics of the stacked packaging structure are optimized by using the orthogonal experimental design method. After further optimization, the junction temperature decreases by 7.17% and the thermal resistance decreases by 11.59%.