A 105–115 GHz Quadrupler MMIC with 4.2 dBm Output Power

This paper presents a 105–115 GHz monolithic quadrupler in
$\boldsymbol{0.25}\ \upmu\mathrm{m}$
GaAs pHEMT technology. The circuit consists of two doubler stages and an intermediate amplifier stage. Coplanar waveguide (CPW) transmission lines and MIM capacitors are utilizing to achieve fundamental, second and fourth harmonic impedance matching. The simulation results demonstrate that the quadrupler achieves a maximum output power of 4.2 dBm from 105 GHz to 115 GHz. The power consumption is 64.2 mW, and the chip size is 1.8 mm
$\times \boldsymbol{0.7}\ \mathbf{mm}^{2}$
. In addition, the suppression of harmonics is better than 20 dBc within the operating band.