Reduced CMV SVPWM Scheme for Three-Level Z-Source NPC Inverter for PV Grid Integration

Renewable energy and various drive applications favor multilevel inverters with voltage boosting capabilities. For those applications, the common mode voltage (CMV) produced by multilevel inverters must be limited. Consequently, a simplified space vector pulse width modulation (SVPWM) scheme for the three-level Z-source neutral point clamping (NPC) inverter with special switching sequences is proposed to achieve voltage boosting and common mode voltage reduction. Three-level SVPWM is implemented using the two-level SVPWMM method to reduce the computational load of dwell time calculations. Restricting CMV to 1/6
^th
of the dc-link voltage requires eliminating small vectors with a higher CMV. The voltage is boosted by inserting shootthrough states into the switching sequences. Harmonics content in the line voltage remains unchanged despite voltage boosting and CMV reduction. The theoretical analysis results are verified in the simulation studies that are conducted in MATLAB/Simulink software.