Performance Evaluation of a Network on Chip Based on Ghz Throughput and Low Power for Streaming Data Transmission on FPGA

Currently, because of how quickly technology is developing, designing sophisticated applications is proving to be very difficult and is leading to issues with throughput, power consumption, chip area, and speed. Reliability and performance become another difficult task when technology production processes progressively scale down to minimise chip dia size. Network on Chip (NoC) is a frequent option in the creation of complicated applications to meet all these challenges in the most recent technological growth. In this study, hybrid approaches NoC are created to optimise the area, throughput, and power consumption. Due to the complexity of using a larger number of routers and the 8×8 dimensions of the NoC in this research project, power consumption is significantly higher with a lower packet delivery ratio. The data transmission between multiple devices in networks with the least amount of latency, memory usage, and power consumption is crucial. Buffered and buffer-less NoC are created utilising Dynamically Reconfigurable NoC (DR-NoC) and the Flexible Direction Order Routing (FDOR) scheme in order to adhere to these restrictions. The FDOR with Transition-Based Power Reduction Encoding (FDOR-TBPRE) Algorithm is presented in order to reduce static power. It can be easily skipped when there are no data or empty buffers, which reduces the dynamic power but leaves static power owing to more transitions in the incoming data. By minimising the amount of transitions in the incoming packets, FDOR-TBPRE is able to deliver higher performance in order to increase energy efficiency, eliminate input buffers, and resolve contention issues. On an 8×8 NoC, the FDOR-performance TBPRE's is verified in terms of power usage, latency, and PDR.