Automated Parasitic-Aware and optimization Tool for CMOS Active Phase Shifters Design

Automatic parasitic-aware simulation-based optimizer for designing PSs is presented in this paper. Knowledge-aware simulation-based optimization and weighting factor methodologies are proposed to reach an optimal and speedy design. The optimization core uses BFGS optimization methodology. Parasitic estimation is done before the sizing process to speed up the design and help obtain an optimum and efficient design. This parasitic estimation is done via a parasitic model generator which models both the interconnects’ effects on active devices and the non-linearities of passive devices. In comparison to the state-of-the-art tools, the presented tool gives limitless solutions when compared to template-based algorithms and a guaranteed converged solution compared to random optimization ones. It uses the mm-wave N-bits digitally controlled active phase shifters (PSs) using the 65nm CMOS technology as a validation of its efficiency. It is noted that it is the first automatic tool used to design active PSs. The output of the tool is generated at the output interface. The outputs are as listed, the circuit schematic, the optimal design parameters, and a generic layout with the GDSII file for any modifications.