TCAD Analysis of Substrate Thickness of a 10nm Vertical Double Gate SOI n-Type MOSFET

This work presents a performance analysis for a 10nm Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and how it changes the characteristics with a change in the substrate thickness. Through this work the best performing design overall are the 4nm and 6nm thicknesses out of Snm, 6nm, 4nm, and 2nm designs tested. The Silicon On Insulator (SOI) technology used here is done for isolation of device from the base substrate. 2nm design shows best on current / off current ratio of approx. 57, but has higher subthreshold slope. Height of the transistor is 34nm from source to drain, and a thickness of 22nm for 8nm substrate and up to 16nm for 2nm substrate. 4nm design is selected as best with a transconductance value of almost 0.002 Ohm-l at a $\mathrm{V}_{\mathrm{D}\mathrm{D}}$ of 1 Volt and at gate voltage of 0.9 Volt. On current of the 4nm design is highest at 1. 06mA. The 2nm design has lowest on current due to resistance of the silicon. Work function of 4.5 is used.