Verification of Burst Transfers in AMBA5-AHB Protocol

Advanced high performance Bus (AHB5) is a signature part of Advanced Microcontroller Bus Architecture (AMBA) family conventions. AMBA5 AHB serve as a bus interface suitable for high-performance synthetic designs. AHB5 will support only single-master designs. The Master is responsible for transportation on the high performance Bus which supports Write, Read, locked, waited and burst transfers. In this paper it is mainly focused on different burst transfers. The basic point of the proposed work is to plan and review the various functional aspect of the protocol. i.e. information read from a specific system area is the similar to the information written to the particular system area and the protocol checks the feature by passing a random values for single address location, random values for randomized indexed address and grouping write and read values together. The design and test are programmed using system Verilog language using Aldec Riviera pro simulator.