Implementation of 3-Bit Reconfigurable Intelligent Surface (RIS) for Sub-6 GHz Range Based on Modified Square loop FSS and Tunable Varactors

In this article, a 3-bit Reconfigurable Intelligent Surface (RIS) based metasurface is implemented for 3.5 GHz sub-6 GHz applications. The unitcell consists of a modified square loop Frequency Selective Surface (FSS) printed on top of a 1 mm thin low-loss grounded dielectric substrate. Two vias are introduced at the centre of the square patch for the reflection phase optimization and HF tunable varactor diodes whose junction capacitance strongly influences the applied voltage. A total of eight different phase states were shown from -180° to 135° insteps of 45°, and the process behind the information encoding for 5G wireless applications is detailed. The angular stability of the reflection phase is investigated for different oblique incidences, and a considerably stable response is observed. Simulated surface current patterns are visualized at resonant frequency for understanding reflection phenomena. The design is compact with a periodicity of 0.058λ
L
×0.058λ
L
and possesses a low-profile thickness of 0.012λ
L
. Authors believe this design has many beneficial features like 3-bit information encoding, angular stability, and compact architecture that play key roles in the RIS design in real-time 5G wireless applications.