Bit Wise Multipliers Using Symmetric Stackers

All computing units, including the Digital Signal Processing (DSP) applications, Multiply Accumulate Unit (MAU), and Arithmetic Logic Unit (ALU), require high speed multipliers. The efficiency of data multiplication is a common performance limiter for DSP systems. Therefore, there is a great need right now for multiplier algorithms that are fast and consume less energy. The design of fast and speed efficient multipliers based on symmetric stacking-based binary counters. This study analyses a Wallace tree multiplier using symmetric stacking-based counters as well as traditional counters. In terms of latency and area, the performance is also contrasted. Verilog HDL and Xilinx are used in programming and synthesis.