High Speed and Low Power Modified Dynamic Double Tail Comparator on 90nm Technology using Cadence

The utilisation of high-speed software would be severely constrained if appropriate comparators were not available. As a consequence of this, there is a growing demand for a comparator that is capable of minimising the amount of power it consumes while maintaining a high level of speed. The consistent application of a double-tail comparator does not have an appreciable impact on the amount of time or effort required to finish a particular task. An adiabatic logic circuit is utilised in the functioning of the double-tail comparator that is described here. It is common knowledge that the type of logic circuit being discussed here has an exceptionally low rate of power consumption. By utilising adiabatic logic and making certain that the transistors utilised in the comparators are of the appropriate size, it is possible to significantly cut down on the amount of power that a device consumes. In spite of a supply voltage that is too low, the comparator is able to keep its high speeds thanks to its relatively low power consumption. It is possible to significantly increase the speed of the device by modifying the proposed comparator design so that it incorporates both a preamplifier stage and a latching stage. With the assistance of Cadence's tools, a simulation of the design is executed utilising CMOS technology at a resolution of 90 nm. This is done so that the results of the analysis will be as accurate as is practically possible. The primary objective of this paper is to cut down on the amount of power that a modified double-tail comparator uses and the amount of time it takes to implement it so that it can be used in high-speed applications. In light of this new information, we need to think creatively if we want to accomplish what we set out to do.