An Enhanced Clock Tree Synthesis Methodology for Optimizing Power in Physical Design

In VLSI industry, power, performance and area are defined as the cost functions which impacts the quality of the product. Physical design, usualy called the backend of the VLSI design deals with stages like floorplanning, Placement, Clock-Tree Synthesis, Routing, STA and other SignOff checks. Among these different stages, CTS stage is one of the prominent stages where the EDA tool builds a clock network for millions and billions of cells. Major power consumption of the design is consumed and controlled by CTS stage since the network drives the entire collection of cells. Hence proper floorplanning, placement and designing a healthy clock-tree helps in optimizing the design to greater heights. In this paper, for the design, two types clock-trees were built, namely a conventional one and Multi-point CTS. Analysing the results and comparing both the methods, an enhanced CTS methodology is proposed where we have overtaken the demerits of the former methods by further optimizing the PPA factors. The enhanced methodology is developed with a idea to reduce clock power consumption by systematically reducing the number of clock cells sitting in the clock path. The paper not only discusses about the steps in CTS stages, but it also explains the various steps in floorplanning and placement stages to give the reader a deep overview about the PD flow.