Residue adder design for the modulo set {2n − 1, 2n, 2n+1 − 1} and its application in DCT architecture for HEVC

Modulo adders are the standard building blocks of Residue Number System (RNS)-based applications. Traditional modulo adders use an end-around carry strategy and a parallel prefix adder that consumes a lot of space. In this paper, a hardware architecture with a low-area and low-power is suggested for the modulo adder with the modulo set P = {2
ⁿ
− 1; 2
ⁿ
; 2
ⁿ⁺¹
− 1}. Experiments show that suggested architecture performs approximately 92% and 26% better than standard architectures in terms of power usage and area consumption, respectively. Its application in the High Efficiency Video Coding (HEVC), Transform module (DCT) is also discussed. When compared to current ones in the literature, the proposed RNS adder-designed 1D-DCT architecture has an area improvement of 18