A Modular Scan Design Verification approach for Multi-channel Mode

This paper proposes a novelty by automating the Scan Design Verification process in DFT. A robust mechanism to move the stimulus control from internal of the design to the external entity is developed. Stimulus engine is used to drive the data at the bump/pin level. During the multichannel scan mode, the dummy flops are inserted into the design in the path: IO Bumps → DDR flyovers input → Routing Fabric input → Tile channels → Routing Fabric output → DDR output → IO Bumps. Since the SoC chip design is dynamic and manual changes are prone to error in the scan verification process, this research work follows ODT (OpenDocument Text Document) based mechanism to define the scan path and presents an automatic solution for Scan Design Verification instead of manually updating the setup every time a new change is made in the design. These channels are mapped to the external pins and the objective is to drive the signals from these pins. This process aids in reducing the time to market in the design verification process by reducing the manual effort/time.