A Time-Based Digital Interface for RF and Baseband IC

In this paper, we propose a digital interface between RF and baseband IC in 5G system. The interface is based on a source synchronous clocking as in DDR (Double Data Rate). This interface provides a constant group delay and a simplified retransmission scheme. There are two different data types: one is a lossy data; the other is a reliable data. To handle both types, we provides two types of data path: Default path and Safe path. The data lane is a single ended; the clock signal is differential signal. The max data rate per lane is 6.6Gbps. The area of 8 lanes for downlink and 4 lanes for uplink is about 1.1 mm
²
at 4 nm process. The power efficiency is 6.8pJ/bit.