Assistant Cache design to minimize SoC System Bandwidth inefficiency caused by Partial Traffic of Legacy Reused IP

This paper presents a method of minimizing inefficiency of SoC system bandwidth that generated from reused Legacy IP through an Assistant Cache with flexible line size. As the size of a system command granule has been increased to maximize performance, the partial traffic of reused IP causes system inefficiency. Since modification of these verified IP requires huge effort to prove it in field again, this paper suggests an approach to reduce this inefficiency by applying the assistant cache at system level while ensuring the existing integrity of IP. In a case study included, the system traffic of a Multi Format Decoder IP is analyzed to make a suitable architecture, and the effect of that for both system bandwidth and IP performance are analyzed under various configurations. Consequently, 45% of effective system bandwidth was saved and the average response time was short to 40% faster at 4% area increasing.