Fabrication and Electrical Measurements of CMOS-integrated GM-APDs and Test Structures in 180nm CMOS Technology Platform

This paper presents the fabrication, TCAD simulation and electrical characterization activities carried out in the development of Geiger mode APDs (GM-APDs) utilizing SCL’s 180nm CMOS process. Two additional mask-steps and a custom anneal cycle was integrated into standard CMOS flow for the fabrication of GM-APDs. Custom anneal cycle was introduced in such a way that thermal budget of CMOS process was not disturbed. Fabricated SiPM device (array size: 1.5x1.5 mm
²
, pixel size: 35x35 um
²
, No. of pixel: 1156) exhibited dark current (at < VBD) is less than 10nA/cm
^-2
. Process splits were implemented to analyse the effect of implant dose on breakdown (BD) voltage and measured breakdown voltage ranges from 15 to 21V. These splits were supported by 2D TCAD process and device simulation. 61% and 23% geometrical fill factor was achieved for 35x35 um
²
and 10x10 um
²
pixel size respectively. Standard CMOS p-well implant (over trench) was used to separate adjacent pixels. Test structures were also characterized to establish relation between edge breakdown voltage and n+/isolation p-well implant separation. The distance between n+ and isolation p-well contributes in dead area which affects the fill factor of the devices. Functionality of the device was verified by the dark events observed in digital oscilloscope. DCR of a SPAD measured less than 20 cps/um
²
at 1V excess bias.