An Efficient Low-Power VIP-based VC Router Architecture for Mesh-based NoC

Network-on-Chip is an emerging paradigm in the domain of multi-processors wherein interconnected patterns were constructed. Numerous problems with traffic congestion, power consumption, and throughput are present because of the sophisticated routing networks, which negatively impact network performance. This research introduces the virtual channel router technique named VIP-based VC router that contains parallel queues in the input buffer which helps in resolving the deadlocks, low power consumption, high throughput and enhances system performance. The proposed technique is applicable to the 8-bit systems, 16-bit systems, and 32-bit systems. The proposed routing technique is assessed on various workloads and the simulation was carried out through the Booksim simulator. The experimental results outperform with enhanced system performance in terms of high throughput and low power consumption when compared with the wormhole router architecture.