Design of Sample and Hold Circuit with Improved Charge Leakage and Linearity for Low Power Applications

This paper presents a novel sample and hold (S/H) circuit for improving charge leakage problem which leads to better linearity. Design of cascaded simple switch is a vital attribute in the proposed circuit. In this work, various sample and hold circuits are simulated using LTSPICE XVII, in 180nm TSMC technology and their performances are examined. The results show that the proposed design is a better choice for front end design of biomedical or sensor applications. From the simulation results, it is observed that the proposed cascaded S/H circuit with boosted driver consumes 2.02 nW of power at 1 V supply voltage. In addition, Signal-to-noise plus distortion ratio (SNDR) of 87.288 dB is achieved for 200 Hz input signal with 250 KS/s sampling rate.