Comparative performance analysis of FinFET, CNTFET and GNRFET for low power digital logic circuit applications

Power dissipation is one of the critical considerations while designing CMOS VLSI circuits for battery- and externally-powered embedded computer applications. This paper discusses a collection of methods that are well-suited for CMOS technology and are easily applicable to VLSI systems and circuit designers specifically for digital logic circuits, SRAM cells and Ternary Logic Gates. Supply-voltage-scaled CMOS is described as a low-power method for digital logic that provides a flexible design space for balancing energy (and power) consumption with circuit speed. Decoders are essential for VLSI and consideration for low power devices is in high demand as portability and battery become a challenge these days. In this paper, a review of techniques and circuits used for ternary logic gates is presented. Also, decoders using GNRFET and FinFET are simulated using HSPICE Tool. Scaling traditional complementary metal-oxide semiconductors (CMOS) has been plagued by issues such as the short channel effect and leakage power. Many transistors based on FinFET, GNRFETs, and DGFETs technologies are used to improve the performance metrics like power consumption, delay, IC area etc. Also, a comparative analysis shows a reduction in power of the order of 102 with 14T and 15T GNRFET based decoder over the MOSFET counterpart.