A Novel 2D Mapping Scheme for Nearest Neighbor Design of Quantum Circuits

In the last few years, quantum computing has gained the attention of the researchers due to its ability to perform parallel and exponentially faster computation over classical computing. One of the prominent challenges for quantum circuits is to satisfy the nearest neighbor (NN) condition, i.e., the qubits of the computing gate must be placed adjacent. Based on this fact, here, in this paper, we have proposed a heuristic synthesis workflow to realize NN circuits in 2D grid configuration. The implemented approach has been evaluated over a broad range of benchmark circuits and we have reported the best results. To validate the efficiency of the stated approach, we have compared it with the previously reported works, an average improvement of 15.94%, 8.89% and 10.98% are obtained over the existing 2D works, and 44.72% and 70.35% are obtained over existing 1D works, respectively.