A Low-Power Counter-based Digital CDR

This paper presents a counter-based digital CDR. For frequency acquisition, frequency direction is determined by comparing the number of edges of input data and recovered data. And for fine frequency acquisition, FLL gain is reduced by counting the number of times as the direction signal changes. The proposed digital CDR is designed and simulated in a 28nm CMOS technology and consumes 6.5mW in 1V supply voltage with 10Gb/s input data.