An Approximate Ternary Full Adder using Carbon nanotube field effect transistors

Multi-valued logic (MVL) is becoming popular because it has potential to reduce area, interconnect, pin count and hence energy than binary logic. The energy efficiency and chip area of ternary circuits can be further improved by employing approximate computing principles in error-tolerant applications. This paper proposes a dynamic approximate ternary full adder that uses only 64 and 66 Carbon nanotube field effect transistors (CNTFET) by exploiting its multi-threshold capabilities through the control of diameter of its nanotubes. The circuit has low transistor count, power, delay and PDP as compared to the exact ternary adder at the cost of inaccurate Sum output for some of the input combinations. This approximate full adder may be used in the lower significant trit positions of an n-bit adder in applications which tolerate small errors without significant degradation in performance.