Design of Low Leakage Radiation Hardened 13T SRAM Cell

This paper presents a 13 Transistor, single bitline radiation hardened SRAM cell (hereafter, referred to as RH13T). Attributed to the single bitline structure, the proposed cell consumes smaller power and the presence of stacked NMOS and PMOS transistors in the design enables it to sustain higher value of charge deposition at its sensitive nodes. RH13T cell offers better critical charge, stability and power dissipation, at the cost of delay penalty, than the cells considered for comparison in this work. We use HSPICE simulations with 65nm PTM model for the analysis and comparison of SRAM cells. The proposed RH13T cell demonstrates critical charge that is 69.64%, 2.64% and 1.82% higher and Hold Static Noise Margin (HSNM) which is 142%, 20% and 19.766% higher than the conventional 6T, AS8T and AS10T SRAM cells respectively. We observe that RH13T offers reduction in write power of 74.72%, 77.23% and 78.408% and reduction in read power of 12.66%, 13.103% and 41.128% and reduction in leakage power of 18.51%, 23.23% and 32.36% when compared to conventional 6T, AS8T and AS10T SRAM cells respectively. Therefore, the proposed RH13T could be an option for low power radiation hardened applications.