Efficient Multiplication and Accumulation of Signed Numbers

Multiply and Accumulate (MAC) is an essential operation for domain-specific hardware accelerators used in the application domains such as digital signal processing, image processing, and artificial intelligence. Moreover, in artificial intelligence or machine learning accelerators, many inputs and weights need to be multiplied and accumulated in parallel to increase the performance. In this paper, we consider the problem of multiplying 32 pairs of 8-bit signed numbers and accumulating them in parallel. We use the Radix-4 Booth algorithm to generate the partial product rows for all 32 pairs of operands and group similar partial product rows as a set. Further, each set is compressed using a customized signed Wallace tree until two rows, which are added using a carry-lookahead adder. Our customized Wallace tree shows 1.3 x area improvement and reduced delay compared to a standard reduction tree when synthesized using a 5 nm process node's standard cell libraries. The proposed MAC design is also 5 % area-efficient compared to a compiler optimized MAC design.