Stacked Multi-layer Zig-Zag On-chip Inductor

In this paper, high performance stacked multilayer zig-zag on-chip inductor for 5G applications is proposed. The proposed multilayer inductor is designed and simulated using Agency Workers Regulations (AWR). The stacked zig-zag inductor shows a minimum improvement of 160% in terms of quality factor and 24% in terms of inductance over the range of 10–75 GHz frequencies with respect to stacked planar inductor. The proposed stacked multilayer zig-zag inductor shows an improvement greater than 120% in terms of both the quality factor and inductance over the range of 10–30 GHz frequencies with respect to stacked multilayer planar inductor and occupies on-chip area of 100μm×100μm suitable for RF applications.