Performance Comparison of Circular Double Gate Transistor (CDGT) with Novel Architectures for High-Performance Applications

In this study, a detailed analysis of an enclosed layout circular double gate transistor (CDGT) at a gate length of 12 nm for High-Performance (HP) applications is presented. Further, we analyzed the performance comparison against existing novel architectures such as FinFET, Nanowire (NW), and Nanosheet (NS) devices. The performance metrics like ON-current (I
ON
), I
ON
/I
OFF
ratio, device leakage current (I
OFF
), and subthreshold slope (SS) are considered during the comparison. The presented CDGT device has a high ON-current of
$4923 \mu \mathrm{A}/\mu \mathrm{m}(5.62\times 10^{- 4}\ \mathrm{A})$
, which is ∼7 times more than the next best device (NS FET). The influence of source/drain doping concentration variations has also been investigated on all these devices. The proposed CDGT device is a suitable substitute for the NS FET in HP applications by offering a higher ON-current (I
ON
) for future technology nodes.