Fault Tolerant Technique for Processor Control Path to Mitigate SEUs in FPGA

Single-Event-Upset is a transient fault that occurs during the lifetime of the circuit operation. These faults lead to system failure if it occurs in machine-critical applications. Multiple SRAM-based Field Programmable gateway (FPGA) is made available with the in-built processor for designing adaptive hardware systems. Faults in the control path of the processor lead to system failure as it changes the instruction itself. This paper proposes a novel solution to mitigate the single event upsets in the control paths of the processor by introducing a novel encoding technique for the control path element of the processor. The proposed techniques are verified on Proasic3e FPGA and compared with traditional mitization techniques.