Static Timing Analysis of Multibit Flipflop based LFSR

In the emerging VLSI technologies the industries demand for low power, area and to avoid timing violations in the digital circuits. The setup and hold timing turned out to be one of the important parameters analysed during the design of the clock routes for the digital circuits. Linear feedback shift register is a circuit used mainly in the testpattern generators. Designing a normal 8-bit LFSR will require 8 D flipflops. A major goal is to achieve a functionality of 8-bit LFSR using the 4 multibit flipflops which in turn reduces the area, power and the number of the clock routes. Reducing the number of clock routes will reduce number of violations occuring in path. The analysis of the setup and hold violations were performed for both 8-bit LFSR and multibit based LFSR using Xilinx Vivado tool in prelayout stage and seen that the timing violations for multibit based LFSR which has 3 violations with slack −0.042 ns is much lesser than 8 bit LFSR which has 11 violations with slack −3.708 ns.