A 6-bit 2GS/s Flash ADC with Low Power Consumption

This paper describes the design of a 6-bit 2GS/s flash analog-to-digital converter (ADC) which is composed of a resistance divided network, comparators, and a 6-bit encoder. The ADC works under a supply voltage of 1.5 V and a sampling frequency of 2 GS/s. The simulation result based on DAC quantization shows that the DNL and INL are below 0.42 LSB and 0.29 LSB. The SFDR and SNDR have reached 47.28 dB and 33.64 dB when the frequency of the input sinusoidal signal is 2.44 MHz. The ADC is designed in TSMC 65 nm technology and only consumes 8.87 mW working at a sampling frequency of 2 GS/s. The layout of the design is also proposed.