New insights on the excess 1/f noise at cryogenic temperatures in 28 nm CMOS and Ge MOSFETs for quantum computing applications

Cryo-CMOS characterization, modeling, and development have significantly progressed to help overcome the interconnection bottleneck between qubits and the readout interface of quantum computers. Nevertheless, available compact models for circuit design fail to predict the detrimental deviation of 1/f noise from the expected T scaling observed at cryogenic temperatures. In this paper, we extensively characterize noise on a commercial 28 nm CMOS technology as well as on Ge channel devices at temperatures ranging from 370 K down to 4 K. Our investigations give fundamental insights into the origin of the excess 1/f noise at low temperatures by excluding electron heating and bulk dielectric defects as possible causes. We show further evidence for a strong correlation between the excess 1/f noise and the saturation of the subthreshold swing (SS). A plausible cause of the excess noise is found in disorder-induced states in the channel acting as new trapping centers at cryogenic temperatures. Random telegraph noise (RTN) waveforms and power spectral density (PSD) measurements on small area MOSFETs support this explanation.