Area and Power Efficient 8K Real-Time Design for AV1 Arithmetic Decoding

The increasing demand for video media over limited bandwidth is currently an issue for both industry and academia. In the face of that challenge, AV1 is a recent video codec designed to compress videos efficiently. As the first step of AV1 playback, the codec utilizes a multi-alphabet arithmetic decoder as the entropy decoder kernel, with up to sixteen symbols. Hence, to accomplish a compromise trade-off between area, power, and real-time performance, we proposed MultiAD, an AV1 arithmetic decoder architecture. The presented design can decode a symbol of an alphabet with up to four elements in a single cycle, requiring more cycles for larger alphabets. When compared to the baseline prior-art architecture, MultiAD saves up to 58.3% in area and consumes 62.1% less power, while still accomplishing the 8K real-time video processing constraints.