The Need for 2-Phase Design Paradigms in High-Throughput GALS Network-On-Chip Architectures

In modern computer chips, the communication infrastructure interconnecting IP cores is usually implemented as a network-on-chip (NoC) with packet switching protocol, instead of conventional bus-based communication. NoC has been widely used as a standard to achieve scalability and modularity, as well as acceptable throughput and power efficiency for complex multi-core chip designs. However, as manufacturing technology continues to scale down to the ever-smaller sub-micron region, synchronization with a central clock signal has become an increasingly critical challenge for such development. An effective solution is to utilize a Globally-Asynchronous Locally-Synchronous (GALS) architecture model, in which IP cores are made by conventional synchronous logic while the NoC is usually constructed by asynchronous quasi-delay-insensitive (QDI) paradigms. This paper will describe that GALS NoC design style and provide a comprehensive review of both existing 4-phase and 2-phase QDI methodologies for its implementation. The limitations of 4-phase approaches will be examined in particular, as will the need for more efficient 2-phase templates. To fill the gap, a novel 2-phase design methodology is proposed, along with its latest progress.