Study on Substrate Crack through Experiment and Simulation on SSD BGA under Temperature Cycling

This paper provides a comprehensive overview of typical substrate crack failure modes under harsh temperature cycling test (TCT). Design features associated with substrate crack are summarized based on experiment observation. A global-local finite element modeling (FEM) approach is illustrated to address crack incidents from die side and ball side of substrate, respectively. Soldermask and copper trace stress and strain response are iterated under TCT condition with plastic behavior considered. Good agreement is seen between simulation high stress region and actual crack location in experiment. Simulation DOE study is performed to examine different substrate structure and substrate materials that could potentially prolong solder mask and copper trace crack performance.