Thin Memory Chip Fabrication for Multi-stack Hybrid Bonding Applications

Hybrid bonding with 3D stacking of thin chips for high bandwidth memory is a widely explored packaging technology. In this study, thin memory wafer fabrication is demonstrated for multichip stacking applications of up to four chips using the hybrid bonding technology. For the first time, damascene fabrication processes have been established and optimized for 50 µm thickness temporary bonded wafers. The test vehicle was designed with a chip size of 13 × 6 mm and a substrate size of 15 × 8 mm. The minimum trace width and spacing in the routing layers is 2/2 µm. The hybrid bonding pad is designed with 5 µm and 3 µm in diameter while the pitches are maintained at 10 µm and 6 µm respectively. Test chips and substrates are designed for back-to-face bonding, and for chip backside, both inorganic and organic dielectric materials are evaluated. Memory chip stacking was evaluated using dielectric materials to identify the assembly process window establishment and mechanical integrity of the stacking.