Low Power Explicit-Pulsed Single-Phase-Clocking Dual-edge-triggering Pulsed Latch Using Transmission Gate

F1ip-flops/pulsed latches are one of the main contributors of power consumption in modern processors including GPU/AI processors. In this paper, a novel Low-Power Explicit-Pulsed Single-Phase-clock Dual-edge-triggering (LPP DET) Pulsed Latch using Transmission-gate is proposed. A novel XOR-based-circuit is used to detect input changes, create adaptive pulses, and eliminate redundant switching. In terms of power consumption, the LPP DET outperforms prior state-of-the-art DET, FS TSPC, by about 33.1% at 10% data switching activity and 1V in 45 nm technology using post-layout simulation.

I. Introduction

Power consumption has been one of the top concerns for modern processors including GPU/AI processors. Inside modern processor, the clocking system, which is composed of a clock distribution network and flip-flops (FFs)/Pulsed latches [1–12], can consume more than 50% of the total power [1].