Research on Glitch Power Estimation of Combinational Logic Circuits

Aiming at the problem that glitch power consumption is ignorant when evaluating power consumption at the earlier stage, especially at register-transfer-level, this paper proposes a method to estimate the glitch at the logic synthesis stage. This method analyzes the factors affecting the glitch and creates a prediction model based on the simulation data of the glitch and the random forest regression algorithm. The experimental results show that the error of the glitch prediction is within 20% at the logic synthesis stage.